It's extremely frustrating that these fast models are very old at this point. Chat jimmy launched in february, and nothing has come of it, not even GA let alone improvements with intelligence.
AI is currently moving so fast, that might as well be a lifetime.
We get SOTA from anthropic/openai every few weeks on models that seem to focus on one useful thing (e.g. opus) and then 5 useless things like booking restuarants. We're ignoring really useful applications for some reason.
It took jev to shake things up. I remember seeing reactions that were basically "people want this? the big labs probably have some version of this lying around"... and it's like yea, maybe these labs need to fix their priorities a little bit.
That has never been made available even to limited customers as far as reporting goes. Currently available ultrafast on GPT-6 Astra and GPT-6.1 Sol are all using Nvidia for good reason [0].
The fact that Cerebras, which has a willing and major customer like OpenAI begging at their heels to deploy on their hardware, now posts about a 2.8T open weight model says a lot.
For some reason though on openrouter the tps of 6.1 sol ultrafast is usually lower than opus 5.5 fast. Is there readings off as surely cerebras hardware is faster than low user density nvidia still?
GPT-6.1 Sol Ultrafast also uses Nvidia hardware, not Cerebras, just far better provisioned vs how they usually provide inference allowing for higher throughput.
I was a subscriber of their now-unavailable coding plan. The 1000 TPS was very unique at the time, but nowadays their qwen 3.8 gets roflstomped by Mercury 3 at both cost and performance at similar TPS speed. There's not much reason to use them unless you're an enterprise with a custom deal.
Qwen3.8 27B is a dense model with expensive K/V caching. It's fantastic if you have 32-48GB of VRAM and want to run 1 or 2 agent sessions locally. But if serving batch inference for many users, it's expensive.
DeepSeek V4 Flash 0731 is dirt cheap at scale, less than 10% of the cost of Qwen3.8 27B. This is because it's an MoE and it uses much less VRAM for KV cache. And it's generally a better model. V4.1 is also cheap at scale, though I've heard mixed reports on the optimized K/V caching.
You should not be running Qwen3.8 27B on an API normally. Maybe Cerberas's hardware is bad at batching or supporting more efficient K/V caching schemes, or something like that?
If you have 48GB of VRAM, you should be able to get Qwen3.8-Flash-Next running and from my use, it's basically the tipping point. 27B is great for a bit of work, but I have QFN running non stop (when I can gather the correct ideas for it to implement).
Ah, this prompted a few questions from me. Perhaps someone with more hardware background could chime in.
They don't really show it here, but supposedly a Cerebras' chip is sub-divided into a 2D mesh of what they call PEs (cores). So data flow generally flows in two axis, and maintains consistent timings to its 4 neighboring cores. They show the layers flowing from left-to-right being streamed by PEs, but I wonder how true that ends up being: maybe the communications are easier to stream via diagonals, or some other shape that has better topology for data flow.
Then, even from die shots of CPUs and GPUs we often see that cores are tiled as squares, and those don't have the same cross-core connection and streaming requirement. Now, I assume that some parts of what we call a core can be moved around more freely while maintaining whatever power/heating/timing requirements we have, so perhaps it's easier to 'force' a square by moving those loose parts around. But why do we confine those to squares? Is super-core layout just something not worth investing time into, like how interconnects are timed, non-convex tilings, and distances to I/O?
And for streaming architectures like Cerebras, why aren't other types of tilings considered, something like a hexagon grid? This could have 3 inputs / 3 outputs, which could allow more complex data flow (?). Similarly, we could have 8 connections with longer diagonals in a square tiling, etc.
I guess, what are the tradeoffs in place such that so many chip designs seem to reuse square tilings both locally and globally?
The reason 2D grids work well is because you can split tensor axes along whatever dim you want across PEs (batch, sequence, hidden, etc.). And your per PE code is relatively simple. It's of the type : get data from neighbor, compute my subtensor, send to neighbor. And you can implement broadcasts and reductions along any axis.
The EDA tools that are used to design chips do not support diagonal wires so that kind of rules out hexagonal grids. With only horizontal and vertical wires you end up with rectangular/square grids or rings.
If that is so, would it be entirely to decrease search space for layout algorithms? I believe there isn't anything in the fabrication process that couldn't model diagonals.
I could see that square packing is more simple, but by shifting elements per row I don't see why it couldn't propagate at odd angles.
Are the next generation of Cerebras chips designed by the current generation? Maybe it won't be recognizable as a particular layout but rather a chaotic but functional vibe layout.
They've shown the calculation for number of concurrent requests limited by kv cache size. I guess for each new request loaded into the queue, the kv cache for that context will need to be loaded from a supporting storage server, that will need to have a lot of ram to store the active caches of multiple requests?
Less "storage server" and more "attention server".
A server that both holds KV cache in its own memory, and uses its own compute to perform attention operations. That way, you don't have to transfer cache entries server to server for every attention sweep - only the "requests" and "responses". Attention bandwidth stays server-local.
> The total number of concurrent requests represents the number of simultaneous requests moving through the pipeline at any point in time. Unlike a GPU batch, those requests don’t wait for one another to finish, they stream through the pipeline continuously.
What do they mean by “unlike a GPU batch”? It’s not a hardware limitation of GPUs right? It’s just the scaffolding to do this in software isn’t available right
It's describing a different type of parallelism - pipeline parallelism. The network is laid out spatially on the wafer in CB's case. So weights are stationary and activations flow. A GPU is going to process the network one layer at a time. GPUs also use other types of parallelism (tensor and expert mainly in inference). Pipeline parallelism doesn't make much sense on a GPU for inference.
I think the point is they need several wafers to fit the model. Data parallelism between requires too much bandwidth (they only have so much edge real estate for io) so you have to do pipeline parallelism with say one layer per wafer. No one does it on gpu unless you can’t fit the model in one fast network domain (which is 72 GPUs nowadays for Nvidia). There is a Dwarkesh episode from like two months ago that explains this reasonably accurately.
From reading xpct's comment in this thread it seems like they use effectively a very deep and wide pipeline by tiling the cores without central clocking or dispatch. In theory if a GPU is centrally organized it could simulate this behaviour, but I imagine that creates transfer overhead. Just speculating though.
I tried Cerebras this week for my project and their 27b model at 2000tks would be perfect for it. Unfortunately it doesn't do the 2k tokens per second which is what I am looking for.
I will check it out! I am using that exact model and it is very verbose when compared with the latest Muse, for example, increasing the completion time a bit too much.
It's not launched yet and 2k isn't a hard requirement but faster inference of relatively simple prompts make a big difference for us. Cerebras also failed because it has very small context window.
And the fact that you will never be benefited from the batching they’ve explained either, you’ll be paying for every token sequential or parallel unlike nvidia or amd gpus
"X is the Y of Z" might not be insightful enough to prevent being downvoted. It's basically a saying, and the author likely spent like 20 seconds coming up with it. Probably I spent more time just writing this comment, than parent spent thinking+writing theirs.
Insightful critique of AI companies get upvoted here, more so than insightful cheering, I'd say.
A wafer looks pretty big. I'm surprised it has only 44GB of memory available. Doesn't that seem a tad .... low? I'm not a hardware person, but I would have assumed much more memory would fit into a wafer?
IMO the next big shift in AI hardware is when some of the upcoming logic-compatible memory types mature. Inference inherently likes many small local pools of memory, with their own interface each. This is impractical with currently available memory other than sram.
At 20 kW average consumption per WSE-3T wafer this gives roughly 1.18 MW for the whole system. Assuming 1500 tokens per second and 190 concurrent requests this gives 4.1 J/token. Which is good I suppose for the size of the model?
For a fairly weak comparison, modern Bitcoin mining chips are around 13J/TH, so around 0.32TH per token, or 320 billion double-sha256 mining operations per token served by this system. Peanuts are also about 4200 Joules, or almost exactly 1000 tokens per nut assuming you could efficiently turn it into electricity to run this chip. Just as a frame of reference, I don't think this actually serves to make any point.
Extreme speeds are actually interesting if you think about it. We are apparently getting some interesting results from LLMs nowadays. If they would put 100x effort in 10% the time it takes, or imagine 1% where how long tool calls take become the bottleneck, that would actually probably feel like a really special kind of "super intelligence".
I think that just like there's tons of different kind of "superheroes" and nobody disputes whether they're genuinely deserving of the name or not, there could be many valid types of super intelligence.
If something is roughly as intelligent as a normal human expert in a given area, but 100 times faster, that would be a valid example of super intelligence.
I'm sure that by some definitions like this we've already discovered narrow super intelligence.
For example - breadth of knowledge. Is knowledge a kind of intelligence? If so then current agents absolutely have a breadth of knowledge which is superhuman.
More like lighting a fire in your codebase at the speed of light.
Nobody needs this, and the quality of models they're deploying, or all llms for that matter, require heavy human review (if you care at all about maintainability).
One developer can barely keep up with the daily output of multiple llm sessions writing code at 50 tps.
Im convinced anyone confidently thinking 2k tps is a no brainer is probably not concerned about the quality of their work (many such cases).
You’re thinking about this the wrong way. Yes, any individual developer doesn’t need this much power all the time. But any individual developer would like to get an answer quickly, which this does. You share the speed and capacity of this over a whole organization. Any one developer only uses a fraction of its capabilities at any given time. Getting an “instantaneous” answer is quite helpful. Think of it like a shared compiler; a developer is not constantly compiling, but having an “instantaneous” compiler is quite useful.
most of the time developers arn't looking for answers. They want to implement some feature. And I'd hazard most developers arn't using these things as a crafter implementer but a frankenstein of architect, implementer, tester, builder and deployers.
And the dev, if they're sane, wants to actually evaluate what it's doing in those arenas. Speed might be a psychology killer then. Actually being able to see the development process as it does it's good think and it's wrong think is a benefit for local development.
I don't think speed of tokens is all that magical if there's a huge imbalance of ability to "human in the loop" it's processs.
Occasionally it takes me at most 10 minutes to figure out that a solution the LLM took an hour to churn out is not up to par and I need to throw it away entirely.
There are diminishing returns, but half of the rate you mentioned would already help me keep focus.
At those token rates you could treat the LLM as a compiler and rebuild your software from scratch every week. That would mean the end for AI slop because people who spend the effort to build a process that creates high quality software from scratch can take full advantage of the one shot performance of an LLM without having to release the process itself.
Youre completely missing my argument. Speed is not the bottleneck, its the review burden.
You need human review when working on anything not table stakes. You cannot write shitty code for an avionics package on an airplane under the assumption that if we encounter bugs, its no big deal because we can rewrite it super fast..
It seems like all these bullish takes on AI are coming from people who think all software runs in a browser, and simply exists to take stripe payments or serve ads. Most software is actually very high stakes and lives depend on it and have high compliance burdens.
Just because it can "one shot" (which actually means 90 tools calls and a whole lot of brute forcing against tests/linter/compiler, and possibly reward hacking) to something that runs, does not mean it will continue to run well.
People treat llm made software like disposable code. You're the only one using it, typically on a single machine with no real world multi-user testing, but for some reason we derive from the fact it worked well the 3 times we used it, on a single machine with a single user that it is evidence of llm solving programming. Its bogus.
You can lessen the human review burden by pitting multiple agents against each other. Ask 3 agents to implement the same solution, then set them up against each other in differential tests. This can find bugs in them or clarify the spec. When tokens get cheap it is worth having multiple replicas, taking advantage of different programming languages, libraries and agents. You don't keep one version, you have a population, and it tests itself. It's easier to implement again than to imagine testing scenarios anyway.
This is why I think there will be selective pressure for fast tools. It’s like an evolutionary process and fast tools will be preferred and created. It’s already happening and also why I think computer use is a dead end.
Lol these guys have another stupid quantization scheme they had mentioned earlier. Most models are stupider at least from them gateways.
Such a weird company with a terminally online on linkedin ceo, garbage devrel on X. Cant really be friends with CSPs coz everyone has their own chip, no consumer solution either, no neocloud would want to onboard them either coz its baggage no one wants to risk dev time/customer money with.
could push kv-cache to off chip cheaper storage like dram. Inference engine manages decode for a single user to run to completion before decode a different users so kv-cache fetch from dram to sram is limited.
I'd want to know is what a 59-wafer pipeline costs in failure domain. The GPU deployment can lose a node and degrade; Because, here the model is the rack, so one bad wafer takes the whole thing down, and a pipeline that has to be live end to end doesn't get a rolling upgrade. How do you drain one?
When will we see some speed improvements? Opus 5.5 is smart enough now.
Cerebras is good on paper but all I can reasonably access is "GPT OSS 120b, Qwen 3.8 27B" which aren't very good for my use.
Openrouter on nitro gets me there. Although the TPS is 5X less still.
I have tried GPT OSS 120b on cerebras and it flies. But it's mostly wrong.
> GPT OSS 120b
It's extremely frustrating that these fast models are very old at this point. Chat jimmy launched in february, and nothing has come of it, not even GA let alone improvements with intelligence.
AI is currently moving so fast, that might as well be a lifetime.
We get SOTA from anthropic/openai every few weeks on models that seem to focus on one useful thing (e.g. opus) and then 5 useless things like booking restuarants. We're ignoring really useful applications for some reason.
It took jev to shake things up. I remember seeing reactions that were basically "people want this? the big labs probably have some version of this lying around"... and it's like yea, maybe these labs need to fix their priorities a little bit.
GPT-5.6 Sol Ultrafast is running on Cerebras hardware.
That has never been made available even to limited customers as far as reporting goes. Currently available ultrafast on GPT-6 Astra and GPT-6.1 Sol are all using Nvidia for good reason [0].
The fact that Cerebras, which has a willing and major customer like OpenAI begging at their heels to deploy on their hardware, now posts about a 2.8T open weight model says a lot.
[0] https://blogs.nvidia.com/blog/gpus-openai-gpt-6-astra-ultraf...
You can get 6.1 sol on ultrafast.
For some reason though on openrouter the tps of 6.1 sol ultrafast is usually lower than opus 5.5 fast. Is there readings off as surely cerebras hardware is faster than low user density nvidia still?
https://openrouter.ai/openai/gpt-6.1-sol
GPT-6.1 Sol Ultrafast also uses Nvidia hardware, not Cerebras, just far better provisioned vs how they usually provide inference allowing for higher throughput.
So then how is OpenAI using Cerebras? Or are they not?
Or, from a different perspective: who is using Cerebras for what purpose?
Jane Street bought up all of the Cerebras x OpenAI compute I believe. Couldn't find a great source, this tweet has a good few replies citing other sources as well https://x.com/cryptopunk7213/status/2106834536868856223
Oh that would make a lot of sense, basically supply limited.
It is not available to "developers".
Sure it is, you just have to pay for it. TANSTAAFL.
I was a subscriber of their now-unavailable coding plan. The 1000 TPS was very unique at the time, but nowadays their qwen 3.8 gets roflstomped by Mercury 3 at both cost and performance at similar TPS speed. There's not much reason to use them unless you're an enterprise with a custom deal.
Qwen3.8 27B is a dense model with expensive K/V caching. It's fantastic if you have 32-48GB of VRAM and want to run 1 or 2 agent sessions locally. But if serving batch inference for many users, it's expensive.
DeepSeek V4 Flash 0731 is dirt cheap at scale, less than 10% of the cost of Qwen3.8 27B. This is because it's an MoE and it uses much less VRAM for KV cache. And it's generally a better model. V4.1 is also cheap at scale, though I've heard mixed reports on the optimized K/V caching.
You should not be running Qwen3.8 27B on an API normally. Maybe Cerberas's hardware is bad at batching or supporting more efficient K/V caching schemes, or something like that?
If you have 48GB of VRAM, you should be able to get Qwen3.8-Flash-Next running and from my use, it's basically the tipping point. 27B is great for a bit of work, but I have QFN running non stop (when I can gather the correct ideas for it to implement).
What quant and engine are you using? The smallest ones I’m seeing on ollama are > 100GB e.g. https://ollama.com/library/qwen3.8-flash-next/tags
Ah, this prompted a few questions from me. Perhaps someone with more hardware background could chime in.
They don't really show it here, but supposedly a Cerebras' chip is sub-divided into a 2D mesh of what they call PEs (cores). So data flow generally flows in two axis, and maintains consistent timings to its 4 neighboring cores. They show the layers flowing from left-to-right being streamed by PEs, but I wonder how true that ends up being: maybe the communications are easier to stream via diagonals, or some other shape that has better topology for data flow.
Then, even from die shots of CPUs and GPUs we often see that cores are tiled as squares, and those don't have the same cross-core connection and streaming requirement. Now, I assume that some parts of what we call a core can be moved around more freely while maintaining whatever power/heating/timing requirements we have, so perhaps it's easier to 'force' a square by moving those loose parts around. But why do we confine those to squares? Is super-core layout just something not worth investing time into, like how interconnects are timed, non-convex tilings, and distances to I/O?
And for streaming architectures like Cerebras, why aren't other types of tilings considered, something like a hexagon grid? This could have 3 inputs / 3 outputs, which could allow more complex data flow (?). Similarly, we could have 8 connections with longer diagonals in a square tiling, etc.
I guess, what are the tradeoffs in place such that so many chip designs seem to reuse square tilings both locally and globally?
The reason 2D grids work well is because you can split tensor axes along whatever dim you want across PEs (batch, sequence, hidden, etc.). And your per PE code is relatively simple. It's of the type : get data from neighbor, compute my subtensor, send to neighbor. And you can implement broadcasts and reductions along any axis.
You have to route around disabled subchips though.
The EDA tools that are used to design chips do not support diagonal wires so that kind of rules out hexagonal grids. With only horizontal and vertical wires you end up with rectangular/square grids or rings.
Do you need diagonal wires for a topological hexagonal tiling?
Wouldn't a rectangular brick layout be topologically a hexagonal tiling
If that is so, would it be entirely to decrease search space for layout algorithms? I believe there isn't anything in the fabrication process that couldn't model diagonals.
I could see that square packing is more simple, but by shifting elements per row I don't see why it couldn't propagate at odd angles.
That's also my assumption. Place and route has to work out an NP hard problem on billions of wires.
Are the next generation of Cerebras chips designed by the current generation? Maybe it won't be recognizable as a particular layout but rather a chaotic but functional vibe layout.
A few years old now, but their co-founder whiteboards how their chips work https://www.youtube.com/watch?v=7GV_OdqzmIU
Citing full precision benchmarks then just going with 4 bit quants
It's natively Q4.
> For ultrafast latency, only activations need to be passed between the wafers, and this can be done via RDMA over Ethernet.
I believe it for decode but the article says nothing about how they make prefill fast on that interconnect story :/.
They've shown the calculation for number of concurrent requests limited by kv cache size. I guess for each new request loaded into the queue, the kv cache for that context will need to be loaded from a supporting storage server, that will need to have a lot of ram to store the active caches of multiple requests?
Less "storage server" and more "attention server".
A server that both holds KV cache in its own memory, and uses its own compute to perform attention operations. That way, you don't have to transfer cache entries server to server for every attention sweep - only the "requests" and "responses". Attention bandwidth stays server-local.
> The total number of concurrent requests represents the number of simultaneous requests moving through the pipeline at any point in time. Unlike a GPU batch, those requests don’t wait for one another to finish, they stream through the pipeline continuously.
What do they mean by “unlike a GPU batch”? It’s not a hardware limitation of GPUs right? It’s just the scaffolding to do this in software isn’t available right
It's describing a different type of parallelism - pipeline parallelism. The network is laid out spatially on the wafer in CB's case. So weights are stationary and activations flow. A GPU is going to process the network one layer at a time. GPUs also use other types of parallelism (tensor and expert mainly in inference). Pipeline parallelism doesn't make much sense on a GPU for inference.
I think the point is they need several wafers to fit the model. Data parallelism between requires too much bandwidth (they only have so much edge real estate for io) so you have to do pipeline parallelism with say one layer per wafer. No one does it on gpu unless you can’t fit the model in one fast network domain (which is 72 GPUs nowadays for Nvidia). There is a Dwarkesh episode from like two months ago that explains this reasonably accurately.
From reading xpct's comment in this thread it seems like they use effectively a very deep and wide pipeline by tiling the cores without central clocking or dispatch. In theory if a GPU is centrally organized it could simulate this behaviour, but I imagine that creates transfer overhead. Just speculating though.
I tried Cerebras this week for my project and their 27b model at 2000tks would be perfect for it. Unfortunately it doesn't do the 2k tokens per second which is what I am looking for.
We can push 1k tps on our speed lane with the right request parameters with deep seek v4.1 flash. Is 2k a hard requirement?
I will check it out! I am using that exact model and it is very verbose when compared with the latest Muse, for example, increasing the completion time a bit too much.
are you evaluating using OpenRouter.ai or other routers/gateways?
they have never been able to keep up with Groq/Cerebras-level inference speeds for some reason.
I am using opencode and Inception.ai (the fastest so far)
what is a project that requires 2k tokens per second?
It's not launched yet and 2k isn't a hard requirement but faster inference of relatively simple prompts make a big difference for us. Cerebras also failed because it has very small context window.
Well, a weekend project that requires 345'600'000 tokens — you only get so many seconds in two days ;)
What's your use case?
Sorry, can't say just yet but nothing as dramatic as what was guessed below :)
I bet it is large-scale data crunching for labeling or categorization.
Probably not because this is usually not a time sensitive task.
High frequency trading? :)
And the fact that you will never be benefited from the batching they’ve explained either, you’ll be paying for every token sequential or parallel unlike nvidia or amd gpus
Cerebras is the Transmeta of the AI wave.
Not sure why people would downvote this. Your not allowed to criticize any AI company on this site it seems.
"X is the Y of Z" might not be insightful enough to prevent being downvoted. It's basically a saying, and the author likely spent like 20 seconds coming up with it. Probably I spent more time just writing this comment, than parent spent thinking+writing theirs.
Insightful critique of AI companies get upvoted here, more so than insightful cheering, I'd say.
A wafer looks pretty big. I'm surprised it has only 44GB of memory available. Doesn't that seem a tad .... low? I'm not a hardware person, but I would have assumed much more memory would fit into a wafer?
It's SRAM. It's the equivalent of 44 GB of CPU cache.
Exactly, which is why it’s so incredibly fast. And expensive.
traditional SRAM memory has 6 transistors per bit. Dense SRAM can have two transistors.
Wafers can have trillions of transistors, 10-16 times more than the 4 trillion of the WSE-3.
1 Terabyte of SRAM per wafer will be the upper limit for a few years [1].
[1] https://youtu.be/vbqKClBwFwI?si=gbBeZ1B66_eGI81Z
SRAM doesn't shrink as well as other types of circuitry do when process nodes advance.
SRAM is not very dense.
IMO the next big shift in AI hardware is when some of the upcoming logic-compatible memory types mature. Inference inherently likes many small local pools of memory, with their own interface each. This is impractical with currently available memory other than sram.
You mean it is unimaginably massive.
Ok I'm sold, where to buy? :D
If you made the mistake of buying their stock the past few weeks, you might wish you hadn't (or maybe it's an opportunity to buy low yada yada)
Maybe it is the bottom now?
At 20 kW average consumption per WSE-3T wafer this gives roughly 1.18 MW for the whole system. Assuming 1500 tokens per second and 190 concurrent requests this gives 4.1 J/token. Which is good I suppose for the size of the model?
For a fairly weak comparison, modern Bitcoin mining chips are around 13J/TH, so around 0.32TH per token, or 320 billion double-sha256 mining operations per token served by this system. Peanuts are also about 4200 Joules, or almost exactly 1000 tokens per nut assuming you could efficiently turn it into electricity to run this chip. Just as a frame of reference, I don't think this actually serves to make any point.
Pay peanuts, get Shakespeare?
Each Nvidia rack is 120 kilowatts, so the power consumption is about the same as 10 racks of GPUs, FWIW.
Extreme speeds are actually interesting if you think about it. We are apparently getting some interesting results from LLMs nowadays. If they would put 100x effort in 10% the time it takes, or imagine 1% where how long tool calls take become the bottleneck, that would actually probably feel like a really special kind of "super intelligence".
It would absolutely be a phase change in practical utility, but it still wouldn't be "super intelligence".
I think that just like there's tons of different kind of "superheroes" and nobody disputes whether they're genuinely deserving of the name or not, there could be many valid types of super intelligence.
If something is roughly as intelligent as a normal human expert in a given area, but 100 times faster, that would be a valid example of super intelligence.
I'm sure that by some definitions like this we've already discovered narrow super intelligence.
For example - breadth of knowledge. Is knowledge a kind of intelligence? If so then current agents absolutely have a breadth of knowledge which is superhuman.
Or you'd just be making the same mistakes experts do but at a 100x clip.
Tortious really does win the race, and there is no such thing as a free lunch.
It would be a super intelligence in terms of thinking speed, not necessarily be super intelligent, mind you.
More like lighting a fire in your codebase at the speed of light.
Nobody needs this, and the quality of models they're deploying, or all llms for that matter, require heavy human review (if you care at all about maintainability).
One developer can barely keep up with the daily output of multiple llm sessions writing code at 50 tps.
Im convinced anyone confidently thinking 2k tps is a no brainer is probably not concerned about the quality of their work (many such cases).
You’re thinking about this the wrong way. Yes, any individual developer doesn’t need this much power all the time. But any individual developer would like to get an answer quickly, which this does. You share the speed and capacity of this over a whole organization. Any one developer only uses a fraction of its capabilities at any given time. Getting an “instantaneous” answer is quite helpful. Think of it like a shared compiler; a developer is not constantly compiling, but having an “instantaneous” compiler is quite useful.
most of the time developers arn't looking for answers. They want to implement some feature. And I'd hazard most developers arn't using these things as a crafter implementer but a frankenstein of architect, implementer, tester, builder and deployers.
And the dev, if they're sane, wants to actually evaluate what it's doing in those arenas. Speed might be a psychology killer then. Actually being able to see the development process as it does it's good think and it's wrong think is a benefit for local development.
I don't think speed of tokens is all that magical if there's a huge imbalance of ability to "human in the loop" it's processs.
Occasionally it takes me at most 10 minutes to figure out that a solution the LLM took an hour to churn out is not up to par and I need to throw it away entirely.
There are diminishing returns, but half of the rate you mentioned would already help me keep focus.
At those token rates you could treat the LLM as a compiler and rebuild your software from scratch every week. That would mean the end for AI slop because people who spend the effort to build a process that creates high quality software from scratch can take full advantage of the one shot performance of an LLM without having to release the process itself.
Youre completely missing my argument. Speed is not the bottleneck, its the review burden.
You need human review when working on anything not table stakes. You cannot write shitty code for an avionics package on an airplane under the assumption that if we encounter bugs, its no big deal because we can rewrite it super fast..
It seems like all these bullish takes on AI are coming from people who think all software runs in a browser, and simply exists to take stripe payments or serve ads. Most software is actually very high stakes and lives depend on it and have high compliance burdens.
Just because it can "one shot" (which actually means 90 tools calls and a whole lot of brute forcing against tests/linter/compiler, and possibly reward hacking) to something that runs, does not mean it will continue to run well.
People treat llm made software like disposable code. You're the only one using it, typically on a single machine with no real world multi-user testing, but for some reason we derive from the fact it worked well the 3 times we used it, on a single machine with a single user that it is evidence of llm solving programming. Its bogus.
You can lessen the human review burden by pitting multiple agents against each other. Ask 3 agents to implement the same solution, then set them up against each other in differential tests. This can find bugs in them or clarify the spec. When tokens get cheap it is worth having multiple replicas, taking advantage of different programming languages, libraries and agents. You don't keep one version, you have a population, and it tests itself. It's easier to implement again than to imagine testing scenarios anyway.
This is why I think there will be selective pressure for fast tools. It’s like an evolutionary process and fast tools will be preferred and created. It’s already happening and also why I think computer use is a dead end.
Lol these guys have another stupid quantization scheme they had mentioned earlier. Most models are stupider at least from them gateways.
Such a weird company with a terminally online on linkedin ceo, garbage devrel on X. Cant really be friends with CSPs coz everyone has their own chip, no consumer solution either, no neocloud would want to onboard them either coz its baggage no one wants to risk dev time/customer money with.
As far as I understand, they have more demand and commitments than their production and scaling capacity. Maybe they're doing something right.
could push kv-cache to off chip cheaper storage like dram. Inference engine manages decode for a single user to run to completion before decode a different users so kv-cache fetch from dram to sram is limited.
I'd want to know is what a 59-wafer pipeline costs in failure domain. The GPU deployment can lose a node and degrade; Because, here the model is the rack, so one bad wafer takes the whole thing down, and a pipeline that has to be live end to end doesn't get a rolling upgrade. How do you drain one?