The EDA tools also have close relationships with the fabs like TSMC. Their moats aren't necessarily the software, it's that relationship and the ability to update the software for the latest process.
Open source would always be behind, the fabs don't want other fabs knowing about their process which is why its secluded behind the EDA tools with NDAs.
The moat of the closed source EDA tools is the validation hours that went into them.
I use the open source EDA tools for VLSI everyday and I do like them, especially how hackable they are, but they are very unreliable compared to the closed source tools, and that's not the highest bar.
Run time of the open source EDA tools are also very slow for designs over, say, ~250K gates. And that's an issue when in commercial designs the base unit for measuring the number of gates in a macro is megacells, i.e. 10^6 cells. Much of the effort of the commercial tools has just been keeping up with Moore's law which is not easy when many brute-force form EDA algorithms are like n^3 even with heuristics.
but on the other hand, because placement and routing isn't a problem that has an easily calculable solution. Their algorithms and heuristics are their secret sauce. If one is in the lead, it would be a very big step towards helping raise their competitors up to their level. Not that I agree with it, but there you go.
No, their algorithms and heuristics are not especially good.
The reason for their quasi-monopoly is the one stated by another poster, that the 3 big EDA companies have privileged relationships with TSMC and the other major foundries so they have access to information that is not available to anyone who would want to develop alternative EDA tools for state-of-the-art CMOS processes and not for ancient processes down to "28-nm" (i.e. at the level reached in 2011, 15 years ago).
28 nm can be good enough for a lot of things, and that's where open source could eventually become a viable option.
We will eventually reach a point where shrinking transistors provides diminishing returns, which should give open-source tooling and processes more time to close the gap. But we're probably still at least a decade away from seeing how that plays out, and who knows what happens with quantum computing, new materials, 3D integration, or some other semiconductor breakthrough in the meantime.
Even then, I don't think open source necessarily catches the absolute state of the art. Unless a startup fab decides to build its own EDA stack and open-source it as a way to attract customers, there will probably always be some gap between open and commercial tooling. The question is whether that gap eventually stops mattering for most designs
The open source tools are great, I use them every day...however, they are light years away from being feature complete for doing a complex products (synthesis qor, multi clock cts, timing driven placement, upf support, statistical timing, too many features to count)...it's death by a thousand paper cuts. Once all those features have been implemented, the next barrier is to get first class status with foundries who ship the EDA development. Currently most only ship enablement for synopsys and cadedence.
Synopsys, Siemens, and Cadence's EDA tools are the reason for the most part.
They have automated a lot of the really hard work and most the industry is trained on their tools.
I wonder if an Alphabet or an Elon Musk would be willing to buy one of these and open source their software tooling. Same for Xilinx.
Open source tools could grow the market by letting many more creators afford to make designs, effectively commoditizing the manufacturers complement.
The EDA tools also have close relationships with the fabs like TSMC. Their moats aren't necessarily the software, it's that relationship and the ability to update the software for the latest process.
Open source would always be behind, the fabs don't want other fabs knowing about their process which is why its secluded behind the EDA tools with NDAs.
The moat of the closed source EDA tools is the validation hours that went into them.
I use the open source EDA tools for VLSI everyday and I do like them, especially how hackable they are, but they are very unreliable compared to the closed source tools, and that's not the highest bar.
Run time of the open source EDA tools are also very slow for designs over, say, ~250K gates. And that's an issue when in commercial designs the base unit for measuring the number of gates in a macro is megacells, i.e. 10^6 cells. Much of the effort of the commercial tools has just been keeping up with Moore's law which is not easy when many brute-force form EDA algorithms are like n^3 even with heuristics.
Synopsys has a $100B market cap. Why would Alphabet buy them and open source the IP? That makes no economic sense.
but on the other hand, because placement and routing isn't a problem that has an easily calculable solution. Their algorithms and heuristics are their secret sauce. If one is in the lead, it would be a very big step towards helping raise their competitors up to their level. Not that I agree with it, but there you go.
No, their algorithms and heuristics are not especially good.
The reason for their quasi-monopoly is the one stated by another poster, that the 3 big EDA companies have privileged relationships with TSMC and the other major foundries so they have access to information that is not available to anyone who would want to develop alternative EDA tools for state-of-the-art CMOS processes and not for ancient processes down to "28-nm" (i.e. at the level reached in 2011, 15 years ago).
28 nm can be good enough for a lot of things, and that's where open source could eventually become a viable option.
We will eventually reach a point where shrinking transistors provides diminishing returns, which should give open-source tooling and processes more time to close the gap. But we're probably still at least a decade away from seeing how that plays out, and who knows what happens with quantum computing, new materials, 3D integration, or some other semiconductor breakthrough in the meantime.
Even then, I don't think open source necessarily catches the absolute state of the art. Unless a startup fab decides to build its own EDA stack and open-source it as a way to attract customers, there will probably always be some gap between open and commercial tooling. The question is whether that gap eventually stops mattering for most designs
> Unless a startup fab decides to build its own EDA stack and open-source it as a way to attract customers
An excellent insight -- good tooling could be a differentiator for a US fab looking to compete on something besides price.
Xilinx literally was bought and it didn't happen
I think you can get pretty far when it comes to hardware design.
I mean you can download and use verilator, openroad, yosys, ngspice, bsim-cmg, klayout and all this fun stuff.
The big blocker is really pdks. Where are you gonna get something that actually fabs? ASAP7 is just predictive.
And foundries are incredibly geopolitically important so they aint revealing anything.
The open source tools are great, I use them every day...however, they are light years away from being feature complete for doing a complex products (synthesis qor, multi clock cts, timing driven placement, upf support, statistical timing, too many features to count)...it's death by a thousand paper cuts. Once all those features have been implemented, the next barrier is to get first class status with foundries who ship the EDA development. Currently most only ship enablement for synopsys and cadedence.